As the frequencies of modern computers continue to increase, the need to rapidly and accurately transmit data between chip interfaces also increases. To ensure that data is accurately transmitted and received, a clock signal is transmitted along with the data to allow a receiving circuit to determine when to sample the transmitted data (such transmissions are referred to and known in the art as “source synchronous” transmissions).
Typically, to ensure the greatest possibility of accurate data transmission/receipt, it is desirable for the receiving circuit to latch data during the middle of the time period in which the data is valid. In other words, if the transmitted clock signal transitions at the beginning of the time period that the data is valid, there is a likelihood of inaccurate receipt of the data due to timing variations resulting from clock skew, voltage variations, etc. To ensure that the clock signal has integrity and is referenced accurately relative to the data signal, a delay lock loop, or DLL, may be used to regenerate a copy of the clock signal at a fixed phase shift from the original.
FIG. 1 shows a portion of a typical computer system 10. The computer system 10 includes a transmitting circuit 12 and a receiving circuit 14. A data signal, DATA 16, and a clock signal, CLOCK 18, form a transmission link between the transmitting and receiving circuits 12 and 14. Data from the transmitting circuit 12 is transmitted to the receiving circuit 14 on the data signal 16, and the corresponding reference clock signal is transmitted from the transmitting circuit 12 to the receiving circuit 14 on the clock signal 18. Those skilled in the art will understand that the portion of the computer system 10 shown in FIG. 1 may include additional transmission links, e.g., data signal 13 and clock signal 15, and/or transmission links by which data is transmitted from the receiving circuit 14 to the transmitting circuit 12.
The data and clock signals 16 and 18 are used to transmit information between the transmitting circuit 12 and the receiving circuit 14 under the direction of control signals, CONTROL 20. The control signals 20, transmitted between the transmitting and receiving circuits 12 and 14, may help determine on which cycle, at what frequency, and/or under which operating mode the data and clock signals 16 and 18 should be transmitted. For example, the control signals 20 may transmit a request that the transmitting circuit 12 transmit a predetermined test pattern to the receiving circuit 14 to test and improve transmission between the transmitting and receiving circuits 12 and 14.
FIG. 2 shows the receiving circuit 14 of FIG. 1 in more detail. The receiving circuit 14 has a latch 32 and a DLL 34. The DLL 34 receives the clock signal 18 and generates a buffered, delayed copy of the clock signal 18, which then serves as a clock input to the latch 32. When toggled, the latch 32, which receives the data signal 16, latches the data signal 16 and outputs the latched data signal as a data signal, CHIP_DATA 36, that is used by the computer system (not shown).
As mentioned earlier, because of the large amounts of data transmitted across chip interfaces, it is important to make sure that data is transmitted accurately. Accordingly, designers have implemented techniques by which transmission links, and hence, data communications, are calibrated at system startup. However, after the system has been operational for some amount of time, data transmission may not be optimal due to changing system conditions, e.g., thermal and voltage gradients. Recalibration of transmission links during operation is prohibitively difficult because of the indeterministic amounts of data being transmitted. Thus, in such cases, optimal data transmission performance may not be achieved.